HCPL-0201资料

H

Low Input Current Logic GateOptocouplersTechnical Data

HCPL-2200HCPL-2219

Features

• 2.5 kV/µs Minimum CommonMode Rejection (CMR) atVCM = 400 V (HCPL-2219)• Compatible with LSTTL,TTL, and CMOS Logic

• Wide VCC Range (4.5 to 20V)• 2.5 Mbd Guaranteed overTemperature

• Low Input Current (1.6 mA)• Three State Output (NoPullup Resistor Required)• Guaranteed Performancefrom 0°C to 85°C• Hysteresis

• Safety Approval

UL Recognized -2500 V rmsfor 1 minuteCSA Approved

VDE 0884 Approved withVIORM = 630 V peak

(HCPL-2219 Option 060Only)

• MIL-STD-1772 VersionAvailable (HCPL-5200/1)

• Ground Loop Elimination• Pulse TransformerReplacement

• Isolated Buss Driver

• High Speed Line Receiver

Description

The HCPL-2200/2219 are

optically coupled logic gates thatcombine a GaAsP LED and anintegrated high gain photo

detector. The detector has a threestate output stage and has a

detector threshold with hysteresis.The three state output eliminatesthe need for a pullup resistor andallows for direct drive of databusses. The hysteresis providesdifferential mode noise immunityand eliminates the potential foroutput signal chatter.

A superior internal shield on theHCPL-2219 guarantees commonmode transient immunity of2.5kV/µs at a common modevoltage of 400 volts.

Functional Diagram

NC1ANODE2CATHODE3NC48VCC7VO6VE5GNDTRUTH TABLE󰀀(POSITIVE LOGIC)LED󰀀OUTPUT󰀀ENABLE󰀀ON󰀀Z󰀀H󰀀OFF󰀀Z󰀀H󰀀ON󰀀H󰀀L󰀀OFFLLSHIELDApplications

• Isolation of High Speed

Logic Systems

• Computer-PeripheralInterfaces

• Microprocessor SystemInterfaces

A 0.1 µF bypass capacitor must be connected between pins 5 and 8.

CAUTION: It is advised that normal static precautions be taken in handling and assembly of thiscomponent to prevent damage and/or degradation which may be induced by ESD.

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5965-3596E

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The Electrical and SwitchingCharacteristics of the HCPL-2200/2219 are guaranteed overthe temperature range of 0°C to85°C and a VCC range of 4.5 voltsto 20 volts. Low IF and wide VCCrange allow compatibility with

TTL, LSTTL, and CMOS logic andresult in lower power consump-tion compared to other high

speed optocouplers. Logic signalsare transmitted with a typicalpropagation delay of 160 nsec.The HCPL-2200/2219 are usefulfor isolating high speed logicinterfaces, buffering of input andoutput lines, and implementingisolated line receivers in highnoise environments.

Selection Guide

Minimum CMRdV/dt(V/µs)1,000VCM(V)50Input On-Current(mA)1.68-Pin DIP (300 Mil)SingleDualChannelChannelPackagePackageHCPL-2200[1]HCPL-2201HCPL-2202HCPL-2231HCPL-2219[1]HCPL-2211HCPL-2212HCPL-2232Small-OutlineWidebodySO-8(400 Mil)HermeticSingleSingleSingle and DualChannelChannelChannelPackagePackagePackagesHCPL-0201HCNW22012,5005,000[2]400300[2]1.81.61.61.82.0HCPL-0211HCNW22111,00050HCPL-52XXHCPL-62XXNotes:

1. HCPL-2200/2219 devices include output enable/disable functionality.

2. Minimum CMR of 10 kV/µs with VCM = 1000 V can be achieved with input current, IF, of 5 mA.

Ordering Information

Specify Part Number followed by Option Number (if desired).Example:

HCPL-2219#XXX060 = VDE 0884 VIORM = 630 Vpeak Option*300 = Gull Wing Surface Mount Option500 = Tape and Reel Packaging Option

Option data sheets available. Contact your Hewlett-Packard sales representative or authorized distributor forinformation.

*For HCPL-2219 only.

Schematic

IF+VF–2ICC8IOIE76SHIELD5VCCVOVEGND31-121

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Package Outline Drawings

8-Pin DIP Package

9.65 ± 0.25(0.380 ± 0.010)TYPE NUMBER8765OPTION CODE*DATE CODE7.62 ± 0.25(0.300 ± 0.010)6.35 ± 0.25(0.250 ± 0.010)HP XXXXZYYWW11.19 (0.047) MAX.234ULRECOGNITION1.78 (0.070) MAX.+ 0.0760.2- 0.051

+ 0.003)(0.010- 0.002)

5° TYP.4.70 (0.185) MAX.0.51 (0.020) MIN.2.92 (0.115) MIN.DIMENSIONS IN MILLIMETERS AND (INCHES).

*MARKING CODE LETTER FOR OPTION NUMBERS.\"V\" = OPTION 060

OPTION NUMBERS 300 AND 500 NOT MARKED.

1.080 ± 0.320(0.043 ± 0.013)0.65 (0.025) MAX.RU2. ± 0.25(0.100 ± 0.010)8-Pin DIP Package with Gull Wing Surface Mount Option 300

PAD LOCATION (FOR REFERENCE ONLY)9.65 ± 0.25󰀀(0.380 ± 0.010)87651.016 (0.040)󰀀1.194 (0.047)6.350 ± 0.25󰀀(0.250 ± 0.010)4.826󰀀TYP.(0.190)󰀀9.398 (0.370)󰀀9.906 (0.390)12341.194 (0.047)󰀀1.778 (0.070)1.780󰀀(0.070)󰀀MAX.9.65 ± 0.25󰀀(0.380 ± 0.010)7.62 ± 0.25󰀀(0.300 ± 0.010)0.381 (0.015)󰀀0.635 (0.025)1.19󰀀(0.047)󰀀MAX.4.19󰀀MAX.(0.165)+ 0.076󰀀0.2- 0.051+ 0.003)󰀀(0.010- 0.002)1.080 ± 0.320󰀀(0.043 ± 0.013)0.635 ± 0.130󰀀2.󰀀(0.025 ± 0.005)(0.100)󰀀BSCDIMENSIONS IN MILLIMETERS (INCHES).󰀀LEAD COPLANARITY = 0.10 mm (0.004 INCHES).0.635 ± 0.25󰀀(0.025 ± 0.010)12° NOM.1-122

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Maximum Solder Reflow Thermal Profile

26024022020018016014012010080604020001234567101112∆T = 145°C, 1°C/SEC∆T = 115°C, 0.3°C/SECTEMPERATURE – °C∆T = 100°C, 1.5°C/SECTIME – MINUTESNote: Use of nonchlorine activated fluxes is highly recommended.

Regulatory Information

The HCPL-2200/2219 have beenapproved by the followingorganizations:

UL

Recognized under UL 1577,Component RecognitionProgram, File E55361.

CSA

Approved under CSA ComponentAcceptance Notice #5, File CA88324.

VDE

Approved according to VDE

0884/06.92. (HCPL-2219 Option060 Only)

Insulation and Safety Related Specifications

Parameter SymbolValueUnitsConditionsMin. External Air GapL(IO1)7.1mmMeasured from input terminals to output terminals,(External Clearance)shortest distance through air.Min. ExternalL(IO2)7.4mmMeasured from input terminals to output terminals,Tracking Pathshortest distance path along body.(External Creepage)Minimum Internal0.08mmThrough insulation distance, conductor to conductor,Plastic Gapusually the direct distance between the photoemitter(Internal Clearance)and photodetector inside the optocoupler cavity.Tracking ResistanceCTI200VDIN IEC 112/VDE 0303 Part 1(ComparativeTracking Index)Isolation GroupIIIaMaterial Group (DIN VDE 0110, 1/, Table 1)Option 300 - surface mount classification is Class A in accordance with CECC 00802.1-123

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VDE 0884 Insulation Related Characteristics (HCPL-2219 OPTION 060 ONLY)

DescriptionInstallation classification per DIN VDE 0110/1., Table 1for rated mains voltage ≤300 V rmsfor rated mains voltage ≤450 V rmsClimatic ClassificationPollution Degree (DIN VDE 0110/1.)Maximum Working Insulation VoltageInput to Output Test Voltage, Method b*VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec,Partial Discharge < 5 pCInput to Output Test Voltage, Method a*VIORM x 1.5 = VPR, Type and sample test,tm = 60 sec, Partial Discharge < 5 pCHighest Allowable Overvoltage*(Transient Overvoltage, tini = 10 sec)Safety Limiting Values(Maximum values allowed in the event of a failure,also see Figure 12, Thermal Derating curve.)Case TemperatureInput CurrentOutput PowerInsulation Resistance at TS, VIO = 500 VVIORMVPRSymbolCharacteristicI-IVI-III55/85/2126301181V peakV peakUnitsVPR945V peakVIOTM6000V peakIS,INPUTPS,OUTPUTRSTS175230600≥109°CmAmWΩ*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section, (VDE 0884), for adetailed description.

Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits inapplication.

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Absolute Maximum Ratings

(No Derating Required up to 70°C)

Parameter

Storage TemperatureOperating Temperature

Average Forward Input CurrentPeak Transient Input Current(≤1 µs Pulse Width, 300 pps)Reverse Input VoltageAverage Output CurrentSupply Voltage

Three State Enable VoltageOutput Voltage

Total Package Power DissipationLead Solder Temperature

Solder Reflow Temperature Profile

SymbolTSTAIF(AVG)IF(TRAN)

Min.-55-40

Max.12585101.0

Units°C°CmAA

Note1

VR5VIO25mAVCC020VVE-0.520VVO-0.520VPT210mW260°C for 10 sec., 1.6 mm below seating plane

See Package Outline Drawings section

1

Recommended Operating Conditions

ParameterPower Supply VoltageEnable Voltage HighEnable Voltage LowForward Input CurrentForward Input CurrentOperating TemperatureFan Out

SymbolVCCVEHVELIF(ON)IF(OFF)TAN

Min.4.52.001.6*–0

Max.20200.850.185[1]4

UnitsVVVmAmA°CTTL Loads

*The initial switching threshold is 1.6 mA or less. It is recommended that 2.2 mA beused to permit at least a 20% CTR degradation guardband.

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Electrical Specifications

For 0°C ≤TA[1] ≤85°C, 4.5 V ≤VCC ≤20 V, 1.6 mA ≤IF(ON) ≤5 mA, 2.0 V ≤VEH ≤20 V,

0.0 V ≤VEL ≤ 0.8 V, 0 mA ≤IF(OFF) ≤0.1 mA. All Typicals at TA = 25°C, VCC = 5 V, IF(ON) = 3 mA unlessotherwise specified. See Note 7.ParameterSym.Logic LowVOLOutput VoltageLogic HighVOHOutput VoltageOutput LeakageIOHHCurrent (VOUT > VCC)Logic High EnableVoltageLogic Low EnableVoltageLogic High EnableCurrentLogic Low EnableCurrentLogic Low SupplyCurrentLogic High SupplyCurrentHigh ImpedanceState OutputCurrentVEHVELIEHMin.Typ.Max.Units Test Conditions0.5VIOL = 6.4 mA (4 TTL Loads)2.4*1005002.00.8201000.004250-0.324.55.25ICCH2.73.1IOZLIOZH6.07..56.0-202010050020IOSH-10-25IHYSVFBVR∆VF∆TACIN5-1.70.121.51.71.75VµA µAVVµAVEN = 2.7 VµAVEN = 5.5 VµAVEN = 20 V mAVEN = 0.4 V mA mA mA mAµAµAµAµAmAmAmAmAmAVVVCC = 5.5 VVCC = 20 VVCC = 5.5 VVCC = 20 VVO = 0.4 VVO = 2.4 VVO = 5.5 VVO = 20 VVO = VCC = 20 VVCC = 5.5VVCC = 20 VVCC = 5 VTA = 25°CIR = 10 µAIF = 5 mAIF = 5 mA,VO = GND342IF = 0 mAIO = OpenVE = Don’t CareIF = 5 mAIO = OpenVE = Don’t CareVEN = 2 V,IF = 5 mAVEN = 2 V,IF = 5 mA2IOH = -2.6 mA *VOH = VCC - 2.1 VVO = 5.5 VVO = 20 VIF = 5 mAVCC = 4.5 VFig.Note12IELICCLLogic Low ShortCircuit OutputCurrentLogic High ShortCircuit OutputCurrentInput CurrentHysteresisInput ForwardVoltageInput ReverseBreakdown VoltageInput DiodeTemperatureCoefficientInput CapacitanceIOSLVO = VCC = 5.5 VIF = 0 mAmV/°CIF = 5 mA60pFf = 1 MHz, VF = 0 V, Pins 2 and 31-126

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Switching Specifications (AC)

For 0°C ≤TA[1] ≤ 85°C, 4.5 V ≤VCC ≤20 V, 1.6 mA ≤IF(ON) ≤5 mA, 0.0 mA ≤IF(OFF) ≤0.1 mA.All Typicals at TA = 25°C, VCC = 5 V, IF(ON) = 3 mA unless otherwise specified.ParameterPropagation Delay Time toLogic Low Output LevelPropagation Delay Time toLogic High Output LevelOutput Enable Time toLogic HighOutput Enable Time toLogic LowOutput Disable Time fromLogic HighOutput Disable Time fromLogic LowOutput Rise Time (10-90%)Output Fall Time (90-10%)Sym.tPHLtPLHtPZHtPZLtPHZtPLZtrtfMin.Typ.Max.UnitsTest Conditions210nsWithout Peaking Capacitor160300With Peaking Capacitor170nsWithout Peaking Capacitor115300With Peaking Capacitor25ns28105605515nsnsnsnsnsFig.Note5, , 55, 67, 97, 87, 97, 85, 105, 104, 5 ParameterLogic HighCommon ModeTransientImmunityLogic Low

Common ModeTransientImmunity

Sym.|CMH|

DeviceHCPL-2200HCPL-2219

Min.Units

1,000 V/µs2,500 V/µs1,000 V/µs2,500 V/µs

Test Conditions

IF = 1.6 mA

|VCM| = 50 V

VCC = 5 VTA = 25°C

|VCM| = 400 V|VCM| = 50 V|VCM| = 400 V

VF = 0 VVCC = 5 VTA = 25°C

Fig.11Note6

|CML|

HCPL-2200HCPL-2219

116

Package Characteristics

Parameter

Input-Output MomentaryWithstand Voltage*

Input-Output ResistanceInput-Output Capacitance

Sym.VISORI-OCI-O

Min.2500

Typ.

Max.Units

V rms

ΩpF

Test ConditionsRH ≤50%, t = 1 min.,TA = 25°C

VI-O = 500 VDC

f = 1 MHz, VI-O = 0 VDC

Fig.Note

3, 8

33

10120.6

*The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuousvoltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Characteristics Table (if applicable), your equipment levelsafety specification or HP Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage,” publication number 5963-2203E.

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Notes:

1. Derate total package power dissipa-tion, PT, linearly above 70°C free airtemperature at a rate of 4.5mW/°C.2. Duration of output short circuit timeshould not exceed 10 ms.

3. Device considered a two-terminaldevice: pins 1, 2, 3, and 4 shortedtogether and pins 5, 6, 7, and 8shorted together.

4. The tPLH propagation delay is

measured from the 50% point on theleading edge of the input pulse to the1.3 V point on the leading edge of theV –1.0 EG0.9VAICC = 4.5 V󰀀TF = 0 mA󰀀L0.8VOO = 6.4 mAV 0.7TUP0.6TUO0.5 LE0.4VEL0.3 WO0.2L –0.1 LO0V-60-40-20020406080100TA – TEMPERATURE – °CFigure 1. Typical Logic Low OutputVoltage vs. Temperature.1000ATA = 25 °Cm 100– IFTNER10V+FR–UC 1.0DRAW0.1ROF –0.01 FI0.0011.11.21.31.41.5VF – FORWARD VOLTAGE – VFigure 4. Typical Input Diode ForwardCharacteristic.

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output pulse. The tPHL propagationsustained with the output voltage in thedelay is measured from the 50% pointlogic high state (Von the trailing edge of the input pulseO > 2.0 V).7. Use of a 0.1 µF bypass capacitorto the 1.3 V point on the trailing edgeconnected between pins 5 and 8 isof the output pulse.

recommended.

5. When the peaking capacitor is omitted,8. In accordance with UL1577, each

propagation delay times may increaseoptocoupler is proof tested by applyingby 100 ns.

an insulation test voltage ≥3000 V rms6. CML is the maximum rate of rise of thefor one second (leakage detectioncommon mode voltage that can be

current limit, Isustained with the output voltage in theI-O ≤5 µA). This test isperformed before the 100% productionlogic low state (VO < 0.8 V). CMH istest for partial discharge (Method b)the maximum rate of fall of theshown in the VDE 0884 Insulationcommon mode voltage that can be

Characteristics Table, if applicable.

Am 05– TVN-1VCC = 4.5 V󰀀EIRF = 5 mAVTCC = 4.5 VA = 25 °C –RU-2 4ECVG TU-3O = 2.7 VATL3POTIU-4V TOH = -2.6 mAOU L2E-5PVVTUEL-6O = 2.4 VO – H1GOIH-7VIOL = 6.4 mA – H-8O-60-40-20020406080100000.51.01.52.0ITA – TEMPERATURE – °CIF – INPUT CURRENT – mAFigure 2. Typical Logic High OutputFigure 3. Output Voltage vs. ForwardCurrent vs. Temperature.

Input Current.

PULSE GEN.󰀀VCCtr = tf = 5 ns󰀀f = 100 kHz󰀀OUTPUT V10 % DUTY󰀀MONITORING󰀀OCYCLE󰀀HCPL-2200NODE5 VVO = 5 V1VCC8IDF1619 ΩINPUT󰀀27MONITORING󰀀NODE36C2 =󰀀D215 pFR1CGND1 =󰀀455 kΩD3120 pFD4THE PROBE AND JIG CAPACITANCES󰀀ARE INCLUDED IN C1 AND C2.RI󰀀2.15 kΩ1.10 kΩ681 ΩIF (ON)1.6 mA3 mA5 mAALL DIODES ARE 1N916 OR 1N30.INPUT IFI50 % IF (ON)F (ON)0 mAtPLHtPHLOUTPUT󰀀VOHVO1.3 VVOLFigure 5. Test Circuit for tPLH, tPHL, tr, and tf.

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250VCC = 5 V󰀀snC1 (120 pF) PEAKING󰀀I (mA) –CAPACITOR IS USED.󰀀F5 YSEE FIGURE 5.A2003LED1.6 NOIT1501.6󰀀AtPHL3󰀀G5APOR100P – PttPLH50-60-40-20020406080100TA – TEMPERATURE – °CFigure 6. Typical Propagation Delaysvs. Temperature.

sn 100– YCL = 15 pF VA 20 V󰀀CCLED80 N 4.5 VOITA60tPLZGA20 VPOR40P t4.5 VEPZLLBA20NE – p0T-60-40-20020406080100TA – TEMPERATURE – °CFigure 8. Typical Logic Low EnablePropagation Delay vs. Temperature.PULSE󰀀CL= 15 pF INCLUDING PROBE󰀀GENERATOR󰀀AND JIG CAPACITANCES.+5 VZtO = 50 ΩVCCr = tf = 5 nsHCPL-2200VOS11VCC8D1619 ΩIF2736CLD2GND5 kΩD453INPUT VCDMONITORING󰀀4NODES2D1-4 ARE 1N916 OR 1N30.INPUT󰀀3.0 VVE1.3 VtPZLtPLZS1 AND󰀀0 VS2 CLOSEDOUTPUT󰀀VOS1 CLOSED󰀀S2 OPEN1.3 V0.5 V0.5 VVOLOUTPUT󰀀tPZHVO1.3 VVOHS1 OPEN󰀀0 V≈1.5 VS2 CLOSEDtPHZS1 AND󰀀S2 CLOSEDFigure 7. Test Circuit for tPHZ, tPZH, tPLZ, and tPZL.

sn200120 –C L = 15 pFVYCC = 5 V󰀀ALVCCs100C2 = 15 pFEn D150– NEOt20 VPHZMI80ITT A4.5 VLG100LAA60PF ,OEtrRSP20 VI40 RE50 L– Bft ANt,PZH4.5 Vrt20 Et f– P0t-60-40-200204060801000-60-40-20020406080100TA – TEMPERATURE – °CTA – TEMPERATURE – °CFigure 9. Typical Logic High EnableFigure 10. Typical Rise, Fall Time vs.Propagation Delay vs. Temperature.Temperature.

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OUTPUT POWER – PS, INPUT CURRENT – ISHCPL-2200AB123VCCOUTPUT VOMONITORINGNODE0.1 µFBYPASS80070060050040030020010000HCPL-2219 OPTION 060 ONLYPS (mW)IS (mA)VCC8765RINVFF4GNDVCM–PULSE GENERATOR+VCM50 V0 VVOHSWITCH AT A: IF = 1.6 mAVO (MIN.)*SWITCH AT B: IF = 0 mAVO (MAX.)*255075100125150175200TS – CASE TEMPERATURE – °COUTPUT󰀀VOVOLFigure 12. Thermal Derating Curve,Dependence of Safety Limiting Valuewith Case Temperature perVDE0884.

* SEE NOTE 6.Figure 11. Test Circuit for Common Mode Transient Immunity and TypicalWaveforms.

VCC1(+5 V)VCC1(+5 V)1.1kΩ120 pFHCPL-220012DATAINPUTTOTEMPOLEOUTPUTGATE12VCC2(+5 V)DATAOUTPUT120 pF (OPTIONAL*)1.1kΩHCPL-220012VCC876GND5VCC2 (4.5 TO 20 V)VCC876RLCMOSDATAOUTPUT3TTL ORLSTTL4GND5UP TO 16LSTTLLOADSOR 4 TTLLOADSDATAINPUTTOTEMPOLEOUTPUTGATE13TTL ORLSTTL4VCC25 V10 V15 V20 VRL1.1 K2.37 K3.83 K5.11 K2Figure 13. Recommended LSTTL to LSTTL Circuit.Figure 14. LSTTL to CMOS Interface Circuit.

VCC (+5 V)VCC1 (+5 V)1.1 kΩDATA󰀀INPUTTTL OR󰀀LSTTL12D134GNDHCPL-2200VCC8765120 pF (OPTIONAL*)1.1kΩ12HCPL-2200VCC876GND5DATAINPUTOPENCOLLECTORGATE4.7 kΩ3TTL ORLSTTL4D1 (1N4150) REQUIRED FOR󰀀ACTIVE PULL-UP DRIVER.Figure 15. Recommended LED Drive Circuit.

Figure 16. Series LED Drive with Open Collector Gate(4.7 kΩ Resistor Shunts IOH from the LED).

*The 120 pF capacitor may be omitted in applications where 500 ns propagation delay is sufficient.

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