按键控制的分频器

这是一个利用VHDL代码编写通过按键控制的分频器，通过给按键s3、s2、s1、s0赋不同的值，可以使分频器输出不同频率，此代码原用于自制示波器的分频。

源代码如下：

LIBRARY IEEE;

USE IEEE.STD_LOGIC_11.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY DVF2 IS

PORT ( CLK : IN STD_LOGIC;

-- D : IN INTEGER RANGE 0 TO 9; FOUT : OUT STD_LOGIC ); END;

ARCHITECTURE one OF DVF2 IS SIGNAL FULL : STD_LOGIC;

--SIGNAL D : INTEGER RANGE 0 TO 9; BEGIN --D<=5;

P_REG: PROCESS(CLK) VARIABLE CNT8 : INTEGER RANGE 0 TO 9; BEGIN

IF CLK'EVENT AND CLK = '1' THEN IF CNT8 = 9 THEN

CNT8 := 5; --当CNT8计数计满时，输入数据D被同步预置给计数器CNT8 FULL <= '1'; --同时使溢出标志信号FULL输出为高电平 ELSE CNT8 := CNT8 + 1; --否则继续作加1计数

FULL <= '0'; --且输出溢出标志信号FULL为低电平 END IF; END IF;

END PROCESS P_REG ; P_DIV: PROCESS(FULL) VARIABLE CNT2 : STD_LOGIC; BEGIN

IF FULL'EVENT AND FULL = '1' THEN

CNT2 := NOT CNT2; --如果溢出标志信号FULL为高电平，D触发器输出取反 IF CNT2 = '1' THEN FOUT <= '1'; ELSE FOUT <= '0'; END IF; END IF;

END PROCESS P_DIV ; END;

LIBRARY IEEE;

USE IEEE.STD_LOGIC_11.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY DVF5 IS

PORT ( CLK : IN STD_LOGIC;

--D : IN INTEGER RANGE 0 TO 9; FOUT : OUT STD_LOGIC ); END;

ARCHITECTURE two OF DVF5 IS SIGNAL FULL : STD_LOGIC;

-- SIGNAL D : INTEGER RANGE 0 TO 9; BEGIN --D<=8;

P_REG: PROCESS(CLK) VARIABLE CNT8 : INTEGER RANGE 0 TO 9; BEGIN

IF CLK'EVENT AND CLK = '1' THEN IF CNT8 = 9 THEN

CNT8 := 8; --当CNT8计数计满时，输入数据D被同步预置给计数器CNT8 FULL <= '1'; --同时使溢出标志信号FULL输出为高电平 ELSE CNT8 := CNT8 + 1; --否则继续作加1计数

FULL <= '0'; --且输出溢出标志信号FULL为低电平 END IF; END IF;

END PROCESS P_REG ; P_DIV: PROCESS(FULL) VARIABLE CNT2 : STD_LOGIC; BEGIN

IF FULL'EVENT AND FULL = '1' THEN

CNT2 := NOT CNT2; --如果溢出标志信号FULL为高电平，D触发器输出取反 IF CNT2 = '1' THEN FOUT <= '1'; ELSE FOUT <= '0'; END IF; END IF;

END PROCESS P_DIV ; END;

library ieee;

use ieee.std_logic_11.all; use ieee.std_logic_unsigned.all; entity DVF is

port(CLK:in std_logic;

S3,S2,S1,S0:in std_logic; FOUT:out std_logic ); end DVF;

architecture DVF of DVF is

COMPONENT DVF2 IS --元件例化 PORT (CLK : IN STD_LOGIC;

-- D : IN INTEGER RANGE 0 TO 9; FOUT : OUT STD_LOGIC ); END COMPONENT;

COMPONENT DVF5 IS --元件例化

PORT (CLK : IN STD_LOGIC;

-- D : IN INTEGER RANGE 0 TO 9; FOUT : OUT STD_LOGIC ); END COMPONENT; SIGNAL

FOUT1,FOUT2,FOUT3,FOUT4,FOUT5,FOUT6,FOUT7,FOUT8,FOUT9,FOUT10,FOUT11:STD_LOGIC;

BEGIN

U1:DVF2 PORT MAP(CLK,FOUT1); U2:DVF5 PORT MAP(FOUT1,FOUT2); U3:DVF2 PORT MAP(FOUT2,FOUT3); U4:DVF5 PORT MAP(FOUT3,FOUT4); U5:DVF2 PORT MAP(FOUT4,FOUT5); U6:DVF5 PORT MAP(FOUT5,FOUT6); U7:DVF2 PORT MAP(FOUT6,FOUT7); U8:DVF5 PORT MAP(FOUT7,FOUT8); U9:DVF2 PORT MAP(FOUT8,FOUT9); U10:DVF5 PORT MAP(FOUT9,FOUT10); U11:DVF2 PORT MAP(FOUT10,FOUT11); PROCESS(S3,S2,S1,S0) VARIABLE S:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN

S:=S3&S2&S1&S0; CASE S IS

WHEN \"1111\"=>FOUT<=CLK; ----输出60MHZ频率 WHEN \"1110\"=>FOUT<=FOUT1;--输出30MHZ频率 WHEN \"1101\"=>FOUT<=FOUT2;--输出6MHZ频率 WHEN \"1100\"=>FOUT<=FOUT3;--输出3MHZ频率 WHEN \"1011\"=>FOUT<=FOUT4;--输出600KHZ频率 WHEN \"1010\"=>FOUT<=FOUT5;--输出300KHZ频率 WHEN \"1001\"=>FOUT<=FOUT6;--输出60KHZ频率 WHEN \"1000\"=>FOUT<=FOUT7;--输出30KHZ频率 WHEN \"0111\"=>FOUT<=FOUT8;--输出6KHZ频率 WHEN \"0110\"=>FOUT<=FOUT9;--输出3KHZ频率 WHEN \"0101\"=>FOUT<=FOUT10;--输出600HZ频率 WHEN \"0100\"=>FOUT<=FOUT11;--输出300HZ频率 WHEN OTHERS=>FOUT<='0'; END CASE; END PROCESS; END ;