A 6-9GHz UWB Transmitter

A 6-9GHz WiMedia UWB RF Transmitter in 90nm CMOS

Zisan Zhang, Koen Mertens, Marc Tiebout, Staffan Ek Stefano Marsili, Denis Matveev, Christoph Sandner Infineon Technologies Austria, Development Center Villach

Siemensstr. 2, A-9500, Villach, Carinthia, Austria

logic. The IQ divider divides the input clock (12-18GHz) by 2 and generates In-phase (I) and Quadrature (Q) LO signals, then the IQ LO signal is amplified and buffered to the IQ modulator. The IQ modulator consists of I and Q path Gilbert-type up-conversion mixers which get IQ analog baseband signal from external signal source. Outputs of the mixers are combined to a differential RF signal and fed to the RF power amplifier, whose differential outputs are connected to RF measurement equipments via an external BALUN. A 3-wire bus control logic is implemented to control gain settings in the power amplifier, power down and sleep mode in all of the blocks.

I. INTRODUCTION

World-wide regulations allow the use of different radio CTRLspectrum fractions for UWB communications. Compared 3-WIRE BUS REG to the FCC in USA, the regulatory bodies in Europe BBIdecided on more stringent emission masks and specific IMIXrestrictions in bandgroup 1 (3-5GHz) [1]; the frequency 18GHzLO INRFPRFILOrange with unrestricted maximum mean equivalent isotropic radiated power density of -41.3dBm/MHz IQ(similar to the FCC requirements) is from 6 to 8.5GHz DIVonly, mapping to WiMedia bandgroup 3. Whereas in QLORFNJapan and Korea only bandgroup 6 (7-9GHz) is released QMIXunrestrictedly. Thus for UWB systems with worldwide BBQinteroperability the frequency range of 6-9GHz is of most RF TX interest.

Although CMOS UWB transceivers in the bandgroup 1

Fig. 1. UWB RF transmitter block diagram. [2,3] and bandgroup 3 [4] have been developed, operating

at higher frequency (9GHz) and wider bandwidth (3GHz) requires innovative approaches in both concept and design A. IQ Divider and LO Buffer to fulfill the aggravated requirements while keeping power

The IQ divider is a CML latch with resistive load. Main consumption low. In this paper, a low-power, highly linear

design challenge is to meet stringent IQ phase matching

6-9GHz UWB RF transmitter with low spurious emission

requirement of less than 1°, which is derived from the

and small chip area is presented. system requirement on the image rejection ratio. The matching requirement leads to relatively large devices in

Abstract — A 6-9GHz RF transmitter fabricated in a standard digital 90nm CMOS technology and targeted for WiMedia UWB bandgroup 3 and 6 is presented. The transmitter features high linearity, low spurious emission, low power and small chip area. Measured data show -5.7dBm output power, -1.41dBm OIP3, -47dBc LO leakage and -33.8dBc sideband rejection with only 72mW from a 1.2V power supply at a minimal chip area of 0.24mm² active area.

Index Terms — CMOS, IQ divider, LO buffer, active inductor, Up-conversion mixer, IQ modulator, power amplifier, RF Transmitter, UWB, low-voltage, low-power.

II. CIRCUIT DESIGN

The block diagram of the UWB RF transmitter is shown in Fig.1. It consists of IQ divider, LO buffers, IQ modulator and RF power amplifier and 3-wire bus control

the divider, consequently big parasitics, furthermore the high operating frequency makes the IQ divider sensitive to the capacitive load and parasitic capacitances at internal nodes. So special attentions are paid in both design and layout to get good matching and minimize parasitics. The

PA978-1-4244-1808-4/978-1-4244-1809-1/08/$25.00 © 2008 IEEE392008 IEEE Radio Frequency Integrated Circuits Symposium

low-pass poles at the IQ divider output nodes are designed to above 12GHz to avoid sharp roll-off at 9GHz, thus the resistor value is rather small (100 Ohms), and this leads to small LO swing. With these constraints, design of the LO buffers becomes a challenge which is not for the bandgroup1 PHY implementations, because the LO buffer should have small input capacitance (small transistor), on the other hand it should have 6dB voltage gain to provide sufficient LO swing to drive the IQ modulator. In this design, a wide band LO buffer using differential pair with active inductor load is used for the first LO buffer to provide 6dB gain while having relatively small input transistors (40um/90nm in this design). Schematic of the first LO buffer is shown in Fig.2, in which M3 and R1 (M4 and R2) forms an active inductor [5]. The active inductor boosts signal at high frequency by more than 4dB compared to the resistive load and it saves chip area significantly compared to the passive inductor. In addition to this, the LO buffer with inductive load is robust in gain and frequency behavior because both its input and load FETs are the same type of transistors. By using this type of LO buffer, power consumption and chip area is reduced significantly in this transmitter. VDD

R1R2M3VOUT+VIN+

M4VOUT-M1M2VIN-VSSFig. 2. Wideband LO buffer using differential pair with active inductor load

In SoC solution, good LO distribution is the key to success; this is especially important for UWB PHY operating at 9GHz. Even with optimized layout floor plan, it is often unavoidable that there are relatively long lines between LO buffers and mixers, requiring a second LO buffer as a line driver. Targeting final SoC integration, the second LO buffer is included in this design. The second LO buffer is a copy of the first stage of the RF power amplifier described in subsection C. B. Up-conversion Mixer

very power hungry, for the system targeting low-power applications, it is also required to have high conversion gain in the up-conversion mixer. For low-voltage deep sub-micrometer CMOS design, this is a big challenge. Conventional Gilbert-cell mixer can provide high conversion gain but it has poor linearity inherent in the V-to-I conversion of the source-coupled pair. In this design, a highly linear low-voltage V-to-I converter is used to replace the source-coupled pair. The simplified schematic of the whole up-conversion mixer is shown in Fig. 4., in which MA, MB, MC, MD are switching quad in the classical Gilbert-cell mixer. M1 to M8 forms a low-voltage highly linear V-to-I converter [6]. The principle of this circuit is to use current feedback to stabilize the source voltage of M2 (M1, M3), assuming M1,M2 and M3 matched, operating in saturation and they have constant input common mode voltage and a constant tail current, then gm of these transistors are kept constant, thus a linear V-to-I conversion is realized. Compared to other V-to-I converter used in other published up-conversion mixers, this one has the following advantages: (1). highly linear and robust, thanks to the current feedback loop used; (2). fully differential, (3). very low static current in the feedback loop and (4). well suited for low-voltage operation. VDDRF

L1L2 R1

VRF+VRF-

VDDBBMA MBMC MD

VLO+ VLO-M4M5 VC

M1M2M3 VBB+VBB-M6

IC

M7M8

VSS

Fig. 3. High conversion gain highly linear UWB up-conversion mixer

For low-voltage operation and to get relatively high The OFDM UWB up-conversion mixer is required to

have broad band operation and high linearity. conversion gain at high frequencies, passive inductor load

has to be used in this mixer. In order to save chip area, Considering RF amplifiers operating at high frequency are

40

stacked inductors are used. The 0.8nH stacked inductor has a dimension of 50um*30um, which is only 15% percent of a non-stacked inductor with the same inductance. To get 3GHz bandwidth, Q of the inductor is further reduced by a parallel resistor R1. For calibration of LO leakage, artificial DC offset current is added to the converted baseband current by using 6 bits programmable current sources.

This up-conversion mixer is very robust in linearity because of the feedback loop used in the V-to-I converter; and it is also very robust in conversion gain which is mainly determined by the dimension ratio of the same type NMOS transistors (assuming LO swing is fixed). C. RF Power Amplifier

The RF power amplifier (PA) consists of two stages of differential pair with resistive load, whose values are optimized for the amplifiers to have high linearity and a high bandwidth. Each amplifier has its own local biasing block, which is a constant gm biasing with the resistor integrated on chip. As this biasing compensates for transistor and resistor variations over process and temperature, the amplifiers are very robust in gain and linearity.

To get accurate gain control, switchable capacitive voltage divider is inserted between two stages. The capacitive divider array provides attenuations of 16dB in 16 steps with 1dB gain accuracy. Gain can be set by 3-wire bus control registers. Due to the heavy parasitic capacitance of the switchable capacitance array, the resistor in the first stage has to be set to a rather small value of 70Ohm, and the resulting maximum voltage gain of this RF PA is only 0dB, explaining the high conversion gain required in the up-conversion mixer. In order to obtain 1dB inband flatness, special attentions were given to the frequency behavior of each building block.

III. MEASUREMENT RESULTS

Fig. 4. Output spectrum of UWB RF transmitter at maximum output power

Fig. 5. Two-tone test plot of UWB RF transmitter

The fabricated transmitter chip is bonded to a PCB for RF measurements. The differential LO inputs are connected to an RF signal generator via a BALUN. The differential RF outputs are combined to RF measurement equipments via another BALUN. The output spectrum of the transmitter (Fig. 4) shows a maximum output power of -8.6dBm. As the measurement setup (BALUN, cables, connectors, DC-couplers) has -2.9dB insertion loss, the de-embedded maximum output power of this transmitter is -5.7dBm; which is sufficient for short-range applications.

Fig. 6. Inband flatness of UWB RF transmitter at maximum

output power

41

At the maximum output power, this RF transmitter has -33.8dBc sideband rejection; without calibration, it has -35.2dBc LO leakage, after calibration, the LO leakage is suppressed to -47.07dBc. Shown in Fig.5 is the two-tone test result, the measurement was done at 7.5GHz LO signal. With 33MHz and 30MHz two-tone baseband signals, the measured OIP3 value is -1.41dBm. The in-band flatness at maximum output power is shown in Fig.6, the frequency was swept from 5.5GHz to 9.5GHz, from this figure we can see that the ripple is less than 1dB from 6GHz to 8GHz, however it drops by another 2dB from 8GHz to 9GHz. The main reason for the roll-off at high aaa

frequency is the parasitics from the bonding wires and PCB. The measured performance of this transmitter is summarized in the following Table I.

TABLE I

UWB RF TRANSMITTER PERFORMANCE SUMMARY

(marked with “EMPTY”). The used active area are marked with black rectangles, and it is only 0.24mm².

ONCLUSIONIV. Ci i

A 6-9GHz 90nm CMOS RF transmitter targeted for

WiMedia UWB bandgroup 3 and 6 is presented. Operating at 9GHz this transmitter achieves -5.7dBm output power with only 72mW power consumption from a 1.2V supply. By using active inductors and a stacked

inductor, the chip occupies only 0.24mm² of effective

area. These results demonstrate that with innovative approaches in both concept and design, a low-power low-voltage high performance 6-9GHz UWB transmitter is achievable in a deep sub-micrometer standard digital CMOS process.

ACKNOWLEDGEMENT

The authors would like to thank Michael Wassermann,

Parameters Measured Units Sylvia Michaelis, Dietrich Michaelis, Sven Derksen and

Operation Frequency 6-9 GHz

Florian Michl for their assistances and supports.

Maximum Output Power -5.7 dBm Sideband Rejection -33.8 dBc

REFERENCES

LO Leakage -47.07/35.2 dBc With/Without Calibration [1] Commission of the European Communities, “Commission

OIP3 -1.41 dBm decision of 21/II/2007 on allowing the use of the radio Conversion Gain -5 dB spectrum for equipment using ultra-wideband technology in Supply Voltage 1.2 V a harmonised manner in the Community”, Brussels, 21-Feb-2007.(http://ec.europa.eu/information_society/policy/radio_Current consumption 60 mA

spectrum/docs/ref_docs/uwb_04_orig_web.pdf). Effective active area 0.24 mm2

[2] B. Razavi et al., “A 0.13-µm CMOS UWB Transceiver”, Technology Stndrd digitl ISSCC Dig. Tech. Papers, pp. 216-217, Feb., 2005. 90nm CMOS

[3] C. Sandner et al., “A WiMedia/MBOA-compliant CMOS

1mmRF transceiver for UWB”, IEEE Journal of Sold-State Circuits, vol. 41, no. 12, pp.2787–2794, 2006.

[4] J. Bergervoet et al., “A WiMedia-compliant UWB

transceiver in 65nm CMOS”, ISSCC Dig. Tech. Papers,

pp.112-113, Feb 2007.

[5] C.Wu et al., “A 1V 4.2mW Fully Integrated 2.5Gb/s CMOS

Limiting Amplifier using Folded Active Inductors”, Proc.

ISCAS 2004, pp1044-1047, May 2004.

[6] C. Hung et al., “A Low-Voltage Rail-To-Rail CMOS V–I

Converter”, IEEE Trans. on Crcuts and Systems—II:

Analog And Dgtal Sgnal Processng, Vol. 46, No. 6,

pp816-820, June 1999.

[7] M. Arasu et al., “A 3 to 9-GHz Dual-band Up-Converter for

a DS-UWB Transmitter in 0.18-µm CMOS”, IEEE RFIC Fig. 7. Chip photo of UWB RF transmitter

Symposium, pp497-500, June, 2007.

[8] Y. Han et al. “A Low-Power 5GHz Transceiver in 0.13µm Shown in Fig.7 is the chip photo of this transmitter, due

2

CMOS for OFDM Applications with Sub-mm Area”, IEEE to number of test pads and reuse of the designed PCB, a

RFIC Symposium, pp361—3, June, 2007. large part (more than 50%) of the chip area is not used

0.75mm

42