专利名称：High speed counter发明人：HOELZLE, JOSEF申请号：EP00112902.2申请日：20000619公开号：EP1065787A2公开日：20010103
专利附图：
摘要：The clock cycle counting method divides the clock signal by a given division ratioand uses a counter (7) for recording the divided clock signal cycles, the counter indexedby a number of steps corresponding to the division ratio for each clock cycle. The clockcycles of the divided clock signal are analysed to detect a value between 0 and one less
than the division ratio, for delaying the clock signal. A dual counter which is pre- chargedwith a first and/or a second preset value for counting from a first to a second value canbe used.
申请人：INFINEON TECHNOLOGIES AG
地址：St.-Martin-Strasse 53 81541 München DE
国籍：DE
代理机构：Zedlitz, Peter, Dipl.-Inf.
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