IC testing methods and apparatus

专利名称：IC testing methods and apparatus发明人：Tom Waayers,Richard Morren申请号：US12092132申请日：20061018公开号：US07945834B2公开日：20110517

专利附图：

摘要：A testing circuit has scan chain segments () defined between parallel inputs(wpi[] . . . wpi[N−]) and respective parallel outputs (wpo[] . . . wpo[N−]). The scan chainsegments comprise a bank () of cells of a shift register circuit, a core scan chain portion (),a first bypass path around the core scan chain portion () and a second bypass path around

the bank () of cells of the shift register circuit. This architecture enables loading of data inparallel into the core scan chain, or into the shift register (WBR). In addition, each scanchain segment also has a series latching element (), and this provides additional testingcapability. In particular, the shifting of data between the latching elements () can be usedto test the bypass paths while the internal or external mode testing is being carried out.This testing can thus be part of a single ATPG procedure.

申请人：Tom Waayers,Richard Morren

地址：Sint Michielsgestel NL,Waalre NL

国籍：NL,NL

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