System and method for high-speed, synchronized dat

专利名称：System and method for high-speed,

synchronized data communication

发明人：Deog-Kyoon Jeong,Gijung Ahn申请号：US09146818申请日：19980904公开号：US06229859B1公开日：20010508

专利附图：

摘要：A system for transmission and recovery of original digital data includes anencoder, a transmitter, a receiver, a decoder, and an analog phase locked loop. Theanalog phase locked loop supplies a sender's clock to the transmitter and a receiver's

clock to the receiver, where the sender's clock frequency is a first integer multiple of thesystem clock frequency, and the receiver's clock frequency is a second integer multipleof the sender's clock frequency within 0.1% tolerance. In a normal flow situation, dataframes are output by the receiver in alternate cycles of the system clock. In an overflowsituation, data frames are output by the receiver in consecutive cycles of the systemclock. In an underflow situation, data frames are not output by the receiver in consecutivecycles of the system clock.

申请人：SILICON IMAGE, INC.

代理机构：Fenwick & West LLP

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