专利名称：Logic circuit and control apparatus using the
same
发明人：Kanekawa, Nobuyasu,Katsuta, Keiichi,Sakata,
Teruaki,Ikeda, Naohiro,Kurihara,Naoki,Shimamura, Kotaro
申请号：EP13182000.3申请日：20130828公开号：EP2709015B1公开日：20190821
摘要：Test pattern injecting means are synchronized not by providing a commonoperation clock thereto but by synchronizing them to the output timing of functionblocks. By synchronizing the test pattern injecting means to the output timing of thefunction blocks, which has a longer cycle than the operation clock, the effect of thevariation in signal delay (skew) can be reduced.
申请人：Hitachi, Ltd.
代理机构：Mewburn Ellis LLP
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