LCK4801资料

Preliminary Data Sheet

July 2001

LCK4801

Low-Voltage HSTL Differential Clock

General

The LCK4801 is a low-voltage, 3.3V HSTL

differential clock synthesizer. The LCK4801 supports two differential HSTL output pairs with frequencies from 336MHz to 1GHz. The clock is designed to support single and multiple processor systems that require HSTL differential inputs. The LCK4801 contains a fully integrated PLL (phase-locked loop) which multiplies the HSTL_CLK or PECL_CLK input frequency to match individual processor clock

frequencies. The PLL can be bypassed so that the PCLK outputs are fed from the HSTL_CLK or

PECL_CLK input for test purposes. All outputs are powered from a 2V external supply to reduce on-chip power consumption. All outputs are HSTL. The PLL can operate in the internal feedback mode, or in the external feedback mode for board level debugging applications.

Features

ssssss

Two fully selectable clock inputs.Fully integrated PLL.

336MHz to 1GHz output frequencies.HSTL outputs.

HSTL and LVPECL reference clocks.32-pin TQFP package.

Description

PCLK0_EN (PULL-UP)PCLK1_EN (PULL-UP)

TESTM (PULL-UP)PLLREF_EN (PULL-UP)REF_SEL (PULL-UP)HSTL_CLK (PULL-UP)HSTL_CLK (PULL-UP)PECL_CLK (PULL-UP)PECL_CLK (PULL-UP)(PULL-UP)

EXTFB_IN (HSTL)

(PULL-DOWN)

EXTFB_EN (PULL-UP)

EXTFB_OUT (HSTL)

SEL[4:0] (PULL-UP)RESET (PULL-UP)PLL_BYPASS (PULL-UP)2274.a (F)

1001

01

/N

EXTFB_OUT

/M

PLL

01

PCLK0PCLK0 (HSTL)PCLK1PCLK1 (HSTL)

DECODE

Figure 1. LCK4801 Logic Diagram

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LCK4801

Low-Voltage HSTL Differential Clock

Preliminary Data Sheet

July 2001

Description (continued)

2SSNAEP_YFLBET0011LT_RSKKKKSLLHLLLLHLLDDCCCCDDPPVPPPPVV232221201918

17SS252416EXTFB_OUTRESET2615EXTFB_OUTSEL[4]2714VDDHSTLSEL[3]2813EXTFB_INSEL[2]2912EXTFB_INSEL[1]3011EXTFB_ENSEL[0]3110

PECL_CLKVDDA

321234567

PECL_CLK

DDMSNNLKKDTSEEELLVSV__SCCE01___TKKFLLLLETTCCRSSPPHHFigure 2. 32-Pin TQFP

2275 (F)

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Preliminary Data SheetJuly 2001

LCK4801

Low-Voltage HSTL Differential Clock

Pin Information

Table 1. Pin DescriptionPin Number

12345671011121314151617181920212223242526272829303132

Pin NameVDDDTESTMVSSPCLK0_ENPCLK1_ENREF_SELHSTL_CLKHSTL_CLKPECL_CLKPECL_CLKEXTFB_ENEXTFB_INEXTFB_INVDDHSTLEXTFB_OUTEXTFB_OUTVDDHSTLPCLK1PCLK1PCLK0PCLK0VDDHSTLPLLREF_ENPLL_BYPASS

VSSRESETSEL[4]SEL[3]SEL[2]SEL[1]SEL[0]VDDA

I/O1PIGIIIIIIIIIIPOOPOOOOPIIPIIIIIIP

TypePower SupplyLVCMOSGroundLVCMOSLVCMOSLVCMOSDifferential HSTLDifferential HSTL

Description

3.3 V power supply.M divider test pins.Digital ground.PCLK0 enable.PCLK1 enable.

Selects the PLL input reference clock.PLL reference clock input.PLL reference clock input.

Differential LVPECLPLL reference clock input.Differential LVPECLPLL reference clock input.

LVCMOSDifferential HSTLDifferential HSTLPower SupplyDifferential HSTLDifferential HSTLPower SupplyDifferential HSTLDifferential HSTLDifferential HSTLDifferential HSTLPower SupplyLVCMOSLVCMOSGroundLVCMOSLVCMOSLVCMOSLVCMOSLVCMOSLVCMOSPower Supply

External feedback enable.External feedback input.External feedback input.Output buffers power supply.External feedback output clock.External feedback output clock.Output buffers power supply.Output clock 1.Output clock 1.Output clock 0.Output clock 0.

Output buffers power supply.PLL reference enable.Input signal PLL bypass.Analog ground for PLL.PLL bypass reset (for test use).

Selection of input and feedback frequency.Selection of input and feedback frequency.Selection of input and feedback frequency.Selection of input and feedback frequency.Selection of input and feedback frequency.3.3 V filtered for PLL (PLL power supply).

1.P = power, I = input, G = ground, O = output.

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LCK4801

Low-Voltage HSTL Differential Clock

Preliminary Data Sheet

July 2001

Pin Information (continued)

Table 2. Frequency Selection

Selection

400000000000000001111111111111111

300000000111111110000000011111111

200001111000011110000111100001111

100110011001100110011001100110011

001010101010101010101010101010101

Input DivideM55555555555555555555555555555555

Feedback Divide

N2425262728293031323334353637383940414243444748495051525355

PCLK (MHz)

for Given Input Frequency (MHz)70336350337839240204344484624790504518532656055886026166304658672686700714728742756770

100480500520056058060062006606807007207407607808008208408608809009209409609801000NANANANANA

120576600624867269672074476879281684088812936960984NANANANANANANANANANANANANANA

1256006256506757007257507758008258508759009259509751000NANANANANANANANANANANANANANANA

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Preliminary Data SheetJuly 2001

LCK4801

Low-Voltage HSTL Differential Clock

Pin Information (continued)

Table 3. Function Control

Control PinREF_SELTESTMPLLREF_ENPLL_BYPASSEXTFB_ENPCLK0_ENPCLK1_ENRESETSEL[4:0]

HSTL_CLK.

M divider test mode enabled.

Disable the input to the PLL and reset the M divider.

Outputs fed by input reference or M divider.

External feedback enabled.PCLK0 = low, PCLK0 = high.PCLK1 = low, PCLK1 = high.Resets feedback N divider.See Table2 on page4.

0

PECL_CLK.

Reference fed to bypass MUX.Enable the input to the PLL.Outputs fed by VCO.Internal feedback enabled.PCLK0 = high, PCLK0 = low.PCLK1 = high, PCLK1 = low.Feedback enabled.See Table2 on page4.

1

Absolute Maximum Characteristics

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability.Table 4. Absolute Maximum Ratings

ParameterPower SupplyInput VoltageWrite Current

Storage Temperature

SymbolVDDD/VDDAVDDHSTL

VINIINTS

Min–0.5–0.5–0.5–1–50

Typical—————

Max4.44.4VDDD + 0.3

1150

UnitVVmA°C

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LCK4801

Low-Voltage HSTL Differential Clock

Preliminary Data Sheet

July 2001

Electrical Characteristics

Table 5. dc Characteristics

VDDA = VDDD = 3.3 V ± 5%, VDDHSTL = 1.7 V—2.1 V, TA = 0 °C—70 °C.

SymbolVIHVILVCMRVPPVIN (dc)VDIF (dc)VCM (dc)VOHVOLIDDIIDDAIDDOThetaJA

DescriptionInput High VoltageInput Low VoltageInput High Voltage1Input Low Voltage1dc Input Signal Voltagedc Differential Input Voltage

dc Common Mode Input Voltage

Output High VoltageOutput Low VoltageCore Supply CurrentPLL Supply CurrentOutput Supply CurrentJunction to Ambient Thermal Resistance

Min2.00.010.5–0.30.40.4VX + 0.3

0————

1515053Typ———————VX + 0.5VX – 0.5

MaxVDDD0.8VDDD – 0.3

11.451.751.01.4VX – 0.314020——

UnitVVVVVVVVVmAmAmA°C/W

ConditionLVCMOSLVCMOSLVPECLLVPECL2HSTL3HSTL4HSTL5HSTL6,1HSTL6———7—81.dc levels will vary 1:1 with VDDD.

2.VPP characteristics required for ac specifications. Actual tolerance of VPP is 200 mV.3.VIN (dc) specifies maximum dc excursion of each differential input.

4.The VDIF (dc) minimum is calculated by VOH – VOL, where VOH is the true input signal and VOL is the complementary input signal.5.VCM specifies the maximum allowable voltage range of the input signal crosspoint.6.VX is the differential output crosspoint voltage (see Table6 on page7).7.Two PCLK signals to 25 Ω, and one EXTFB signal through 50 Ω.8.1.3 M/s (250 fpm) airflow.

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Preliminary Data SheetJuly 2001

LCK4801

Low-Voltage HSTL Differential Clock

Electrical Characteristics (continued)

Table 6. ac Characteristics

VDDA = VDDD = 3.3 V ± 5%, VDDHSTL = 1.7 V—2.1 V, TA = 0 °C—70 °C.SymbolfreffMAXtsk (o)tjit (0)tjit (cc)

Description

Input FrequencyMaximum Output FrequencySkew Error (PCLK)Phase Jitter (I/O Jitter)Cycle-to-Cycle Jitter (Full Period)

Min—336————0.60.68—

Typ70—125————————

Max—100035

(output period)/2

58—0.910

UnitMHzMHZps—%%VVms

Condition

——1—2—2—2,3—2,4For all HSTL output pairs.For all HSTL output pairs.

—

tjit (1/2 period)Cycle-to-Cycle Jitter

(Half Period)VDIFoutVXtlock

Differential Output Peak-to-Peak SwingDifferential Output Crosspoint VoltageMaximum PLL Lock Time

1.When the phase-locked loop is active but in bypass mode, fref maximum is limited by input the buffer; optimum performance is obtainedfrom PECL input.

2.At differential pair crossover.3.Full PCLK period.4.Half PCLK period.

VDDHSTLVOH

VDIF

VX

VCM

VOLVSS

2276 (F)

Figure 3. HSTL Differential Input Levels

Z = 50 Ω

OUTPUT

RT = 25 Ω

VTT = VSS (GROUND)

2277 (F)

Figure 4. Output Termination and ac Test Reference

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LCK4801

Low-Voltage HSTL Differential Clock

Preliminary Data Sheet

July 2001

Applications

Power Supply Filtering

The LCK4801 is a mixed analog/digital product. Because of this, it exhibits some sensitivities that would not

necessarily be seen on a fully digital product. Analog circuitry is susceptible to random noise, the worst case being when this noise is seen on the power supply pins. The LCK4801 provides separate power supplies for the output buffers (VDDHSTL) and the phase-locked loop (VDDA) of the device in order to isolate the high digital output

switching noise from the internal analog PLL. In a controlled evaluation board environment, this level of isolation is adequate. However, in a digital system, a second level of isolation is suggested.

The easiest way to accomplish this is to add a power supply filter on the VDDA pin of the LCK4801. Figure5 on page9 shows the typical power supply scheme. The filter should be designed in the 10 kHz—1 MHz range, since this is the most likely frequency range to cause spectral content noise.

Note the dc voltage drop between VDDD and VDDA on the power supply filter. Very little dc voltage drop can be tolerated when a 3.3 V VDDD supply is used. The power supply filter in Figure5 must be 5Ω—10Ω in order to meet the drop criteria. The RC filter in Figure5 will provide a broadband filter with approximately 100:1 attenuation above 20 kHz.

The impedance of an individual capacitor begins to appear inductive and increases with frequency as the noise frequency crosses the series resonant point of the capacitor. The parallel capacitor combination ensures that for frequencies much greater than the bandwidth of the PLL there is always a low-impedance path.

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Preliminary Data SheetJuly 2001

LCK4801

Low-Voltage HSTL Differential Clock

Applications (continued)

3.3 V

RS = 5—10 Ω

VDDA

0.01 µF

22 µF

VDDD

0.01 µF

2278 (F)

Figure 5. Power Supply Filter

Although the LCK4801 has an isolated power supply and grounds, as well as fully differential PLL, there still may be applications in which overall performance is being compromised due to system power supply noise. The power supply filter schemes discussed are adequate to eliminate power supply noise problems in most designs.

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LCK4801

Low-Voltage HSTL Differential Clock

Preliminary Data Sheet

July 2001

Outline Diagram

Dimensions are in millimeters.

9.00 ± 0.207.00 ± 0.20PIN #1

IDENTIFIER ZONE

32

25

1.00 REF

0.25

GAGE PLANE

1

24

SEATING PLANE

0.45/0.75

7.00± 0.20

9.00± 0.20

DETAIL A

817

916

0.09/0.200DETAIL A

DETAIL B

1.40 ± 0.05

0.30/0.450.20M1.60 MAX

SEATING PLANE

0.100.80 TYP

0.05/0.15

DETAIL B

12-3076(F)

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Copyright © 2001 Agere Systems Inc.All Rights ReservedPrinted in U.S.A.

July 2001DS01-234HSI