MDT10P7301
1. General Description
This EPROM-Based 8-bit micro-controller uses a fully static CMOS technology process to achieve higher speed and smaller size with the low power consumption and high noise immunity. On chip memory includes 4K words of ROM, and 192 bytes of static RAM.
-CCP1, CCP2, SCM, USAR, USAT A/D converter module:
-5 analog inputs multiplexed into one A/D converter -10-bit resolution TMR0: 8-bit timer/counter
TMR1: 16-bit timer/counter TMR2: 8-bit timer
4 types of oscillator can be selected by
programming option: RC－Low cost RC oscillator
LFXT－Low frequency crystal oscillator XTAL－Standard crystal oscillator HFXT－High frequency crystal oscillator On-chip RC oscillator based Watchdog Timer
(WDT)
22 I/O pins with their own independent
direction control
2. Features
The followings are some of the features on the hardware and software : Fully CMOS static design 8-bit data bus
On chip EPROM size: 4.0 K words Internal RAM size: 192 bytes 37 single word instructions 14-bit instructions 8-level stacks
Operating voltage: 2.5 V ~ 5.5 V (PRD Disable)
4.5 V ~ 5.5 V (PRD Enable)
Operating frequency: DC ~ 20 MHz
The most fast execution time is 200 ns under
20 MHz in all single cycle instructions except the branch instruction
3. Applications
The application areas of this MDT10P7301 range from appliance motor control and high speed auto-motive to low power remote transmitters/receivers, pointing devices, and telecommunications processors, such as Remote
Addressing modes include direct, indirect and controller, small instruments, chargers, toy,
relative addressing modes Power-on Reset
Power edge-detector Reset Power range-detector Reset Sleep Mode for power saving Capture, Compare, PWM module Synchronous serial port with SCM,I2C 11 interrupt sources: -External INT pin
-TMR0 timer, TMR1 timer, TMR2 timer -A/D conversion completion -Port B<7:4> interrupt on change
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automobile and PC peripheral … etc.
P. 2 2008/06 Ver. 1.2
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MDT10P7301
4. Pin Assignment
/MCLR 1
PA0/AIC0 2 PA1/AIC1 3 PA2/AIC2 4 PA3/AIC3/Vref 5 PA4/T0CKI 6 PA5/SS/AIC4 7 VSS 8 OSC1/CLKIN 9 OSC2/CLKOUT 10PC0/T1OSO/T1CKI 11PC1/T1OSI 12PC2/CCP 13PC3/SCK 14
2827262524232221201918171615
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0/INT VDD VSS PC7 PC6
PC5/SDO PC4/SDI
MDT10P7301K11(SKINNY) MDT10P7301S11(SOP) MDT10P7301SS11(SSOP)
5. Order Information
Device
ROM (Words)
RAM (Bytes)
I/O
A/D (10 bits)
Timer(8/16)
CCP
SCM/ USART
PackageSKINNYSOP SSOP MDT10P7301K11 4K 192 225-channel 2/1 2 YES/YESMDT10P7301S11 4K 192 225-channel 2/1 2 YES/YESMDT10P7301SS11 4K 192 225-channel 2/1 2 YES/YES
6. Pin Function Description
Pin Name PA0~PA3, PA5
PA4 PB0~PB7
I/O I/O I/O I/O
Function Description
Port A, TTL input level / Analog input channel PA4, Schmitt Trigger input levels, Open drain output Port B, TTL input level / PB0: External interrupt input PB4~PB7: Interrupt on pin change
PC0~PC7 /MCLR OSC1/CLKIN OSC2/CLKOUT
I/O I I O
Port C, Schmitt Trigger input levels Master Clear, Schmitt Trigger input levels Oscillator Input / external clock input
Oscillator Output / in RC mode, the CLKOUT pin has 1/4 frequency of CLKIN
VDD Power supply VSS Ground
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P. 2 2008/06 Ver. 1.2
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MDT10P7301
7. Memory Map
(A) Register Map
Address Description BANK0 00
Indirect Addressing Register
01 RTCC 02 PCL 03 STATUS 04 MSR 05 Port A 06 Port B 07 Port C 0A PCHLAT 0B INTS 0C PIFB1 0D PIFB2 0E TMR1L 0F TMR1H 10 T1STA 11 TMR2 12 T2STA 13 SCMBUF 14 SCMCTL 15 CCP1L 16 CCP1H 17 CCP1CTL 18 RCSC 19 TXREG 1A RCREG 1B CCP2L 1C CCP2H 1D CCP2CTL This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 3 2008/06 Ver. 1.2
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MDT10P7301
Address Description 1E ADRES 1F ADS0 20~7F
General purpose register
BANK1 01 TMR 05 CPIO A 06 CPIO B 07 CPIO C 0C PIEB1 0D PIEB2 0E PSTA 12 T2PER 14 SCMSTA 18 TXSC 19 BRREG 1E ADRESL 1F ADS1 A0~FF
(1) IAR (Indirect Address Register): R00
(2) RTCC (Real Time Counter/Counter Register): R01
(3) PC (Program Counter): R02, R0A
Write PC --- from PCHLAT Write PC --- from PCHLAT LJUMP, LCALL --- from instruction word RTWI, RET --- from STACK General purpose register
A11 A10~A8 Write PC --- from ALU LJUMP, LCALL --- from instruction word RTWI, RET, RTFI --- from STACK A7~A0 This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 4 2008/06 Ver. 1.2
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MDT10P7301
(4) STATUS (Status register): R03
Bit Symbol 0 C Carry bit 1
HC
Half Carry bit
Function
2 Z Zero bit 3 4 5
/PF /TF RBS0
Power down bit WDT timer overflow bit Register Bank select bit 0: 00h~7Fh (Bank0) 1: 80h~FFh (Bank1)
7~6
--
General purpose bit
(5) MSR (Memory Bank Select Register): R04
Memory Bank Select Register: 0: 00h~7Fh (Bank0) 1: 80h~FFh (Bank1) b7 b6 b5 b4 b3 b2 b1 b0
Indirect Addressing Mode
(6) PORT A: R05
PA5~PA0, I/O Register
(7) PORT B: R06
PB7~PB0, I/O Register
(8) PORT C: R07
PC7~PC0, I/O Register
(9) PCHLAT: R0A
(10) INTS (Interrupt Status Register): R0B
Bit Symbol 0 1 2 3
RBIF INTF TIF RBIE
Function
PORT B change interrupt flag, Set when PB <7:4> inputs change Set when INT interrupt occurs Set when TMR0 overflows 0: Disable PB change interrupt 1: Enable PB change interrupt
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MDT10P7301
Bit Symbol 4
INTS
0: Disable INT interrupt 1: Enable INT interrupt
5
TIS
0: Disable TMR0 interrupt 1: Enable TMR0 interrupt
6
PEIE
0: Disable all peripheral interrupt 1: Enable all peripheral interrupt
7
GIS
0: Disable global interrupt 1: Enable global interrupt
(11) PIFB1 (Peripheral Interrupt Flag Bit): R0C
Bit Symbol 0
TMR1IF
TMR1 interrupt flag 0: TMR1 did not overflow 1: TMR1 overflowed
1
TMR2IF
TMR2 interrupt flag
0: No TMR2 to T2PER match occurred 1: TMR2 to T2PER match occurred
2
CCP1IF
CCP1 interrupt flag
0: No TMR1 capture/compare occurred 1: A TMR1 capture/compare occurred
3
SCMIF
SCM interrupt flag
0: Waiting SCM transmit/receive
1: The SCM transmission/reception is complete
4
TXIF
USART transmit interrupt flag 0: The USART transmit buffer is full 1: The USART transmit buffer is empty
5
RCIF
UASRT receive interrupt flag
0: The USART receive buffer is empty 1: The USART receive buffer is full
6
ADIF
A/D interrupt flag
0: A/D conversion is not complete 1: A/D conversion completed
7 -- Unimplemented
Function Function
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P. 6 2008/06 Ver. 1.2
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MDT10P7301
(12) PIFB2 (Peripheral Interrupt Flag Bit): R0D
Bit Symbol 0
CCP2IF
CCP2 interrupt flag
0: No TMR1 capture/compare occurred 1: A TMR1 capture/compare occurred
7~1 -- Unimplemented
(13) TMR1L: R0E
The LSB of the 16-bit TMR1
(14) TMR1H: R0F
The MSB of the 16-bit TMR1
(15) T1STA: R10
Bit Symbol 0
TMR1ON 0: Stop TMR1
1: Enable TMR1
1
TMR1CLK 0: Internal clock (Fosc/4)
1: External clock from pin PC0
2
/T1SYNC TMR1CLK = 1
0: Synchronize external clock 1: Do not synchronize external clock TMR1CLK = 0 This bit is ignored
3
T1OSCEN 0: TMR1 Oscillator is shut off
1: TMR1 Oscillator is enable
5~4 T1CKPS1 1 1 = 1:8 Prescale value
~
1 0 = 1:4 Prescale value
Function Function
T1CKPS0 0 1 = 1:2 Prescale value
0 0 = 1:1 Prescale value
7~6 -- Unimplemented
(16) TMR2: R11 TMR2 register
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P. 7 2008/06 Ver. 1.2
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MDT10P7301
(17) T2STA: R12
Bit Symbol 1~0 T2CKPS1 0 0 = Prescaler is 1
~
0 1 = Prescaler is 4
Function
T2CKPS0 1 x = Prescaler is 16 2
TMR2ON 0: TMR2 is off
1: TMR2 is on
7~3 -- Unimplemented
(18) SCMBUF: R13
Serial communication port buffer
(19) SCMCTL: R14
Bit Symbol Function
3~0 SCM3 0 0 0 0: SCM master mode, clock = Fosc/4
~ SCM0
0 0 0 1: SCM master mode, clock = Fosc/16 0 0 1 0: SCM master mode, clock = Fosc/64 0 0 1 1: SCM master mode, clock = TMR2 output/2
0 1 0 0: SCM slave mode, clock = SCK pin, /SS control enable 0 1 0 1: SCM slave mode, clock = SCK pin, /SS control disable 0 1 1 0: I2C slave mode, 7 bit address. 0 1 1 1: I2C slave mode, 10 bit address. 1 0 1 1: I2C firmware controlled Master mode.
1 1 1 0: I2C slave mode, 7 bit address with start and stop bit interrupts enabled.
1 1 1 1: I2C slave mode, 10 bit address. with start and stop bit interrupts enabled.
4
CKS
0: Transmit happens on rising edge, receive on falling edge, Idle state for clock is low level.
1: Transmit happens on falling edge, receive on rising edge, Idle state for clock is high level
5
SCMEN
0: Disable SCM, then PC3, PC4, PC5 is I/O port. 1: Enable SCM
6
SCMROI 0: No overflow
1: Overflow
7
WCOL
0: No collision
1: The SCMBUF is written while it is still transmitting the previous word
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P. 8 2008/06 Ver. 1.2
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MDT10P7301
(20) CCP1L: R15
Capture/Compare/PWM LSB
(21) CCP1H: R16
Capture/Compare/PWM MSB
(22) CCP1CTL: R17
Bit Symbol 3~0 CCP1M3 0 0 0 0: CCP1 off
~
0 1 0 0: Capture1 mode, every falling edge 0 1 1 0: Capture1 mode, every 4th rising edge 0 1 1 1: Capture1 mode, every 16th rising edge 1 0 0 0: Compare1 mode, set output on match 1 0 0 1: Compare1 mode, clear output on match
1 0 1 0: Compare1 mode, generate software interrupt on match 1 0 1 1: Compare1 mode, trigger special event 1 1 x x: PWM1 mode
5~4
PWM1LSB These bits are the two LSBs of the PWM1 duty cycle
Function
CCP1M0 0 1 0 1: Capture1 mode, every rising edge
7~6 -- Unimplemented
(23) RCSC: R18
Bit Symbol 0 RX9DF 9th bit of received data 1
OERF
0: No overrun error 1: Overrun error
2
FERF
0: No framing error 1: Framing error
3 -- Unimplemented 4
CRENF
0: Disable continuous receive 1: Enable continuous receive
5
SRENF
0: Disable single receive 1: Enable single receive
6
RX9ENF
0: Select 8-bit reception 1: Select 9-bit reception
7 SPENF
0: Serial port disable 1: Serial port enable
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Function
P. 9 2008/06 Ver. 1.2
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MDT10P7301
(24) TXREG: R19 USART transmit register
(25) RCREG: R1A USART receive register
(26) CCP2L: R1B
Capture/Compare/PWM LSB
(27) CCP2H: R1C
Capture/Compare/PWM MSB
(28) CCP2CTL: R1D
Bit Symbol 3~0 CCP2M3 0 0 0 0: CCP2 off
~
0 1 0 0: Capture2 mode, every falling edge 0 1 1 0: Capture2 mode, every 4th rising edge 0 1 1 1: Capture2 mode, every 16th rising edge 1 0 0 0: Compare2 mode, set output on match 1 0 0 1: Compare2 mode, clear output on match
1 0 1 0: Compare2 mode, generate software interrupt on match 1 0 1 1: Compare2 mode, trigger special event 1 1 x x: PWM2 mode
5~4
PWM2LSB These bits are the two LSBs of the PWM2 duty cycle
Function
CCP2M0 0 1 0 1: Capture2 mode, every rising edge
7~6 -- Unimplemented
(29) ADRES: R1E
A/D result register high byte. The ADRES register is not a writable register.
(30) ADS0 ( A/D Status Register ): R1F
Bit Symbol 0
ADRUN
Function
0: A/D converter module is shut off and consumes no operating current 1: A/D converter module is operating
1 -- Unimplemented 2
GO/DONEB 0: A/D conversion not in progress
1: A/D conversion in progress
5~3
CHS2~0 000: AIC0 001: AIC1 010: AIC2 011: AIC3 100: AIC4
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MDT10P7301
Bit Symbol 7~6
Function
ASCS1-0 00: fosc/2 01: fosc/8 10: fosc/32 11: f RC (*Note)
*Note: determined by OSC mode, HF: fosc/32, XT: fosc/8, RC: fosc/2, LF: fosc/2
(31) TMR (Time Mode Register): R81
Bit Symbol 2~0
PS2~0
Prescaler Value
Function RTCC rate
WDT rate 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128
3 4 5 6 7
PSC TCE TCS IES PBPH
0 0 0 1 : 2 0 0 1 1 : 4 0 1 0 1 : 8 0 1 1 1 : 16
1 : 32 1 0 0
1 0 1 1 : 64 1 1 0 1 : 128 1 1 1 1 : 256
Prescaler assignment bit 0: RTCC
1: Watchdog Timer RTCC signal edge
0: Increment on low-to-high transition on RTCC pin 1: Increment on high-to-low transition on RTCC pin RTCC signal set
0: Internal instruction cycle clock 1: Transition on RTCC pin Interrupt edge select
0: Interrupt on falling edge on PB0 1: Interrupt on rising edge on PB0 PORTB7~0 pull-hi
0: PORTB7~0 pull-hi are enable 1: PORTB7~0 pull-hi are disable
(32) CPIO A (Control Port I/O Mode Register): R85 ＝“0”, I/O pin in output mode; ＝“1”, I/O pin in input mode.
(33) CPIO B (Control Port I/O Mode Register): R86 ＝“0”, I/O pin in output mode; ＝“1”, I/O pin in input mode.
(34) CPIO C (Control Port I/O Mode Register): R87 ＝“0”, I/O pin in output mode; ＝“1”, I/O pin in input mode.
(35) PIEB1: R8C
Bit Symbol 0
TMR1IE
TMR1 interrupt enable bit 0: Disable TMR1 interrupt 1: Enable TMR1 interrupt
Function
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MDT10P7301
Bit Symbol 1
TMR2IE
TMR2 interrupt enable bit 0: Disable TMR2 interrupt 1: Enable TMR2 interrupt
2
CCP1IE
CCP1 interrupt enable bit 0: Disable CCP1 interrupt 1: Enable CCP1 interrupt
3
SCMIE
SCM interrupt enable bit 0: Disable SCM interrupt 1: Enable SCM interrupt
4
TXIE
USART transmit interrupt enable bit 0: Disable the USART transmit interrupt 1: Enable the USART transmit interrupt
5
RCIE
USART receive interrupt enable bit 0: Disable the USART receive interrupt 1: Enable the USART receive interrupt
6
ADIE
A/D interrupt enable bit 0: Disable A/D interrupt 1: Enable A/D interrupt
7 -- Unimplemented
(36) PIEB2: R8D
Bit Symbol 0
CCP2IE
0: Disable CCP2 interrupt 1: Enable CCP2 interrupt
7~1 --
(37) PSTA: R8E
Bit Symbol 0 1
PRDB PORB
Function
0: Power range-detector Reset occurred 1: No Power range-detector Reset Occurred 0: Power on Reset occurred 1: No Power on Reset occurred Unimplemented
Function
Function
7~2 -- Unimplemented
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P. 12 2008/06 Ver. 1.2
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MDT10P7301
(38) T2PER: R92
Timer2 period
(39) SCMSTA: R94
Bit Symbol 0
BF
0: Receive not complete 1: Receive complete
I2C_UA
1
0:Address does not need to be updated.
Function
(10 bit I2C 1:Indicates that the user needs to update the address in the sspadd mode)
register.
0:Write
2 I2C_RWB 1:Read
0:Start bit was not detected last.
3 I2C_START 1:Indicates that a start bit has been detected last. 0:Stop bit was not detected last.
4 I2C_STOP 1:Indicates that a stop bit has been detected last.
0:Indicates that the last byte received or transmitted was address.
5 I2C_DAB 1:Indicates that the last byte received or transmitted was data. 7~6 -- Unimplemented
(40) TXSC: R98
Bit Symbol 0 TX9DF 9th bit of transmit data 1
TSRCF
0: TSR full 1: TSR empty
2
HBRCF
0: Low speed 1: High speed
3 -- Unimplemented 4
UMSF
0: USART asynchronous mode 1: USART synchronous mode
5
TXENF
0: Transmit disable 1: Transmit enable
6
TX9ENF
0: Select 8-bit reception 1: Select 9-bit reception
7 CSSF
(41) BRREG: R99 Baud rate register
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0: Slave mode 1: Master mode
Function
P. 13 2008/06 Ver. 1.2
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MDT10P7301
(42) ADRESL: R9E
A/D result register low byte. The ADRES register is not a writable register.
(43) ADS1 (A/D Status Register): R9F
Bit Symbol
Function
0 0 0: PA0~3,PA5 = analog input. VREF = VDD
0 0 1: PA0~2,PA5 = analog input. PA3 = ref input, VREF = PA3 2~0 PAVM2~0 0 1 0: PA0~3,PA5 = analog input. VREF = VDD
0 1 1: PA0~2,PA5 = analog input. PA3 = ref input, VREF = PA3 1 0 0: PA0, 1, 3 = analog input. PA2, 5 = digital I/O, VREF = VDD 1 0 1: PA0, 1 = analog input. PA2, 5 = digital I/O, VREF = PA3 1 1 x: PA0~3, 5 = digital I/O
6~3 -- Unimplemented 7
(44) Configurable options for EPROM (Set by writer)
Oscillator Type RC Oscillator HFXT Oscillator XTAL Oscillator LFXT Oscillator
Watchdog Timer control
Watchdog timer disable all the time Watchdog timer enable all the time
Power-range control Power-range disable Power-range enable
Oscillator-start Timer control
0ms 75ms
ADFM
0:Align to the left, Bit5~bit0 of ADRESL (R9E) are read as “0” 1:Align to the right, Bit7~bit2 of ADRES (R1E) are read as “0”
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MDT10P7301
Power-edge Detect
PED Disable PED Enable
(B) Program Memory
Address Description 000-FFF Program memory 000
The starting address of power on, external reset or WDT time-out reset.
Security state Security Disable Security Enable
004 Interrupt vector
8. Reset Condition for all Registers
Register Address Power-On Reset, Power range detector
Reset IAR 00h N/A RTCC PC STATUS MSR PORT A PORT B PORT C PCHLAT INTS PIFB1 PIFB2 TMR1L TMR1H T1STA TMR2 T2STA SCMBUF SCMCTL
01h 0Ah,02h 03h 04h 05h 06h 07h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h
xxxx xxxx 0000 0000 0000 0001 1xxx xxxx xxxx --xx xxxx xxxx xxxx xxxx xxxx ---0 0000 0000 000x -000 0000 ---- ---0 xxxx xxxx xxxx xxxx --00 0000 0000 0000 ---- -000 xxxx xxxx 0000 0000
/MCLR or WDT Reset
Wake-up from SLEEP
N/A uuuu uuuu 0000 0000 0000 000# #uuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu ---0 0000 0000 000u -000 0000 ---- ---0 uuuu uuuu uuuu uuuu --uu uuuu 0000 0000 ---- -uuu uuuu uuuu 0000 0000
N/A uuuu uuuu PC+1 000# #uuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu ---u uuuu uuuu uuuu -uuu uuuu ---- ---u uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu ---- -uuu uuuu uuuu uuuu uuuu
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MDT10P7301
Register Address Power-On Reset, Power range detector
Reset CCP1L CCP1H CCP1CTL RCSC TXREG RCREG CCP2L CCP2H CCP2CTL ADRES ADS0 TMR CPIOA CPIOB CPIOC PIEB1 PSTA T2PER SCMSTA TXSC BRREG ADRESL ADS1
15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 81h 85h 86h 87h 8Ch 8Eh 92h 94h 98h 99h 9Eh 9Fh
xxxx xxxx xxxx xxxx --00 0000 0000 -00x 0000 0000 0000 0000 xxxx xxxx xxxx xxxx --00 0000 xxxx xxxx 0000 00-0 1111 1111 --11 1111 1111 1111 1111 1111 -000 0000 ---- --0u 1111 1111 ---- ---0 0000 -010 0000 0000 xxxx xxxx 0--- -000
/MCLR or WDT Reset
Wake-up from SLEEP
uuuu uuuu uuuu uuuu --00 0000 0000 -00x 0000 0000 0000 0000 uuuu uuuu uuuu uuuu --00 0000 uuuu uuuu 0000 00-0 1111 1111 --11 1111 1111 1111 1111 1111 -000 0000 ---- --uu 1111 1111 ---- ---0 0000 -010 0000 0000 uuuu uuuu 0--- -000
uuuu uuuu uuuu uuuu --uu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uu-u uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu -uuu uuuu ---- --uu 1111 1111 ---- ---u uuuu -uuu uuuu uuuu uuuu uuuu u--- -uuu
Note : u＝unchanged, x＝unknown, - ＝unimplemented, read as “0” #＝value depends on the condition of the following table
Condition
/MCLR reset (not during SLEEP) /MCLR reset during SLEEP WDT reset (not during SLEEP) WDT reset during SLEEP Power-on reset
Status: bit 4
u 1 0 0
Status: bit 3
u 0 1 0
PSTA: bit 1
u u u u
PSTA: bit 0
u u u u
1 1 0 x This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
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MDT10P7301
Condition
Power-range reset Status: bit 4
Status: bit 3
PSTA: bit 1
PSTA: bit 0
1 1 u 0 Note : u＝unchanged, x＝unknown, - ＝unimplemented, read as “0”
9. Instruction Set
Instruction Code 010000 00000000 010000 00000001 010000 00000010 010000 00000011 010000 00000100 010000 00000rrr 010001 1rrrrrrr 011000 trrrrrrr 111010 iiiiiiii 010111 trrrrrrr 011001 trrrrrrr 011010 trrrrrrr 011011 trrrrrrr 011100 trrrrrrr 011101 trrrrrrr 011110 trrrrrrr 010010 trrrrrrr 110100 iiiiiiii 010011 trrrrrrr 110101 iiiiiiii 010100 trrrrrrr 110110 iiiiiiii 011111 trrrrrrr 010110 trrrrrrr 010101 trrrrrrr 010000 1xxxxxxx 010001 0rrrrrrr
Mnemonic
Operands NOP CLRWT SLEEP TMODE RET CPIO R STWR R LDR R, t LDWI i SWAPR R, t INCR R, t INCRSZ R, t ADDWR R, t SUBWR R, t DECR R, t DECRSZ R, t ANDWR R, t ANDWI i IORWR R, t IORWI i XORWR R, t XORWI i COMR R, t RRR R, t RLR R, t CLRW CLRR R
No operation Clear Watchdog timer Sleep mode
Load W to TMODE register Return from subroutine Control I/O port register Store W to register Load register Load immediate to W Swap halves register Increment register
Increment register, skip if zero Add W and register Subtract W from register Decrement register
Decrement register, skip if zero AND W and register AND W and immediate Inclu. OR W and register Inclu. OR W and immediate Exclu. OR W and register Exclu. OR W and immediate Complement register Rotate right register Rotate left register Clear working register Clear register
Function Operating Status None 0→WT
0→WT, stop OSCW→TMODE Stack→PC W→CPIO R W→R R→t i→W
[R(0~3) ↔R(4~7)]
→t R + 1→t R + 1→t W + R→t R ﹣W→t or (R+/W+1→t) R ﹣1→t R ﹣1→t R ∩ W→t i ∩ W→W R ∪ W→t i ∪ W→W R ♁ W→t i ♁ W→W /R→t
R(n) →R(n-1), C→R(7), R(0)→CR(n)→r(n+1), C→R(0), R(7)→C0→W 0→R
TF, PF TF, PF None None None None Z None None Z None C, HC, ZC, HC, Z
Z None Z Z Z Z Z Z Z C C Z Z
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 17 2008/06 Ver. 1.2
元器件交易网www.cecb2b.com
MDT10P7301
Instruction Code 0000bb brrrrrrr 0010bb brrrrrrr 0001bb brrrrrrr 0011bb brrrrrrr 100nnn nnnnnnnn 101nnn nnnnnnnn 110111 iiiiiiii 110001 iiiiiiii 111000 iiiiiiii 010000 00001001 Note :
W : Working register b : Bit position
WT : Watchdog timer t : Target TMODE : TMODE mode register 0 : Working register CPIO : Control I/O port register 1 : General register TF : Timer overflow flag R : General register address PF : Power loss flag C : Carry flag PC : Program Counter HC : Half carry OSC : Oscillator Z : Zero flag Inclu. : Inclusive ‘∪’ / : Complement Exclu. : Exclusive ‘♁’ x : Don’t care AND : Logic AND ‘∩’ i : Immediate data ( 8 bits ) n : Immediate address
Mnemonic Operands BCR R, b BSR R, b BTSC R, b BTSS R, b LCALL n LJUMP n ADDWI i RTWI i SUBWI i RTFI
Bit clear Bit set
Bit Test, skip if clear Bit Test, skip if set Long CALL subroutine Long JUMP to address Add immediate to W
Return, place immediate to W Subtract W from immediate Reture from interrupt
0→R(b) 1→R(b) Skip if R(b)=0 Skip if R(b)=1 n→PC,
PC+1→Stack n→PC W+i→W Stack→PC,i→W i-W→W
Stack→PC,1→GIS
None None None None None None C,HC,ZNone C,HC,ZNone
Function Operating Status 10. Electrical Characteristics
*Note: Temperature=25°C 1. Operation Current:
(1) HF (C=10p), WDT – disable, PRD – disable 4M 10M 20M Sleep 2.5V 480uA 1mA 2.1mA 1uA 3.0V 600uA 1.3mA 2.5mA 1uA 4.0V 1mA 2mA 4mA 1uA 5.0V 1.5mA 2.9mA 5.3mA 1uA 5.5V 1.8mA 4mA 6.8mA 1uA These parameters are for reference only.
(2) XT (C=10p), WDT – disable, PRD – disable 1M 4M 10M Sleep 2.5V 130uA 440uA 1mA 1uA 3.0V 160uA 560uA 1.2mA 1uA This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 18 2008/06 Ver. 1.2
元器件交易网www.cecb2b.com
MDT10P7301
1M 4M 10M Sleep 4.0V 400uA 900uA 2mA 1uA 5.0V 700uA 1.3mA 2.8mA 1uA 5.5V 940uA 1.6mA 3.3mA 1uA These parameters are for reference only. (3) LF (C=10p), WDT – disable, PRD – disable 32K 455K 1M Sleep 2.5V 30uA 80uA 170uA 1uA 3.0V 40uA 120uA 210uA 1uA 4.0V 90uA 210uA 420uA 1uA 5.0V 180uA 450uA 600uA 1uA 5.5V 270uA 600uA 900uA 1uA These parameters are for reference only.
(4) RC, WDT – disable, PRD – disable, @VDD = 5.0V
C R Freq. Current 4.7k 11.8M 4mA 10k 5.8M 2mA 3p
47k 1.35M 600uA 100k 644K 400uA 300k 196K 250uA 470k 136K 200uA 4.7k 6M 2.7mA 10k 3.04M 1.5mA 20p
47k 692K 500uA 100k 327K 350uA 300k 98K 250uA 470k 70K 200uA 4.7k 2.18M 1.7mA 10k 1.09M 900uA 100p
47k 240K 300uA 100k 112K 250uA 300k 34K 200uA 470k 25K 200uA This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 19 2008/06 Ver. 1.2
元器件交易网www.cecb2b.com
MDT10P7301
C R Freq. Current 4.7k 963K 1.4mA 10k 464K 700uA 300p
47k 101K 250uA 100k 47K 200uA 300k 14K 200uA 470k 10K 200uA These parameters are for reference only.
(5) RC, WDT – disable, PRD – disable, @VDD = 3.0V
C R Freq. Current 4.7k 11.6M 2mA 10k 6.52M 1.2mA 3p
47k 1.62M 300uA 100k 784K 160uA 300k 242K 60uA 470k 173K 60uA 4.7k 6.88M 1.5mA 10k 3.65M 800uA 20p
47k 868K 170uA 100k 415K 100uA 300k 127K 60uA 470k 91K 60uA 4.7k 2.94M 1mA 10k 1.52M 500uA 100p
47k 348K 120uA 100k 116K 60uA 300k 50K 60uA 470k 36K 60uA 4.7k 1.42M 800uA 10k 724K 400uA 300p
47k 164K 100uA 100k 79K 60uA 300k 24K 60uA 470k 17K 60uA These parameters are for reference only.
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 20 2008/06 Ver. 1.2
元器件交易网www.cecb2b.com
MDT10P7301
2. Input Voltage (VDD = 5V): PA~PC Min Max Vil TTL VSS 0.8V Schmitt trigger VSS 0.6V Vih TTL 3.0V VDD Schmitt trigger 3.8V VDD These parameters are for reference only.
Input Voltage (VDD = 3V): PA~PC Min Max Vil TTL VSS 0.4V Schmitt trigger VSS 0.2V Vih TTL 2.0V VDD Schmitt trigger 2.6V VDD These parameters are for reference only.
3. Output Voltage (VDD = 5V): PA~PC Condition Voh Vol Voh Vol 3.3V 0.9V 4.2V 0.6V Ioh = -20mAIol = 20mA Ioh = -5mAIol = 5mA These parameters are for reference only.
Output Voltage (VDD = 3V): PA~PC Condition Voh Vol Voh Vol 1.6V 0.6V 2.4V 0.5V Ioh = -10mAIol = 10mA Ioh = -5mAIol = 5mA These parameters are for reference only.
4. Output Current (Max.) (VDD = 5V): Current Source current Sink current 25mA 40mA This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 21 2008/06 Ver. 1.2
元器件交易网www.cecb2b.com
MDT10P7301
These parameters are for reference only.
5. The basic WDT time-out cycle time: Time 2.5V 25ms 3.0V 23ms 4.0V 20ms 5.0V 18ms 5.5V 17ms These parameters are for reference only.
6. PRD:
(1) PRD reset voltage: Voltage Vih 4.2V±10% Vil 3.8V±10% These parameters are for reference only.
(2) PRD reset current: Current 5.0V 120uA 4.0V 100uA These parameters are for reference only.
7. Pull high resistor:
VDD 5V 3V PB7~0
50KΩ±20% 100KΩ±20%
These parameters are for reference only.
8. MCLR filter time:
VDD 5V Time 1000ns±20%
These parameters are for reference only.
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 22 2008/06 Ver. 1.2
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